This board allow to manage a FM transmitter including a Phase Locked Loop (PLL)on a serial bus (SPI) like a MC145170.
A current frequency is memorized in EEPROM to configure PLL at power up.
Three auxiliairy frequencies are available for maintenance function and/or HF adjust.
A local interface include 4 keys and a LCD display enable to modify transmitter parameters.
This board can be completely drived from a serial link RS232 (19200 Bds,8b data,2b stop, no parity).
A temperature sensor enable to control working temperature and 2 analog input are used for HF power measure (Forward and Reflected).
Information about TOS protection activation is processed by this board to inform user (local and remote) on a TOS Alarm.
This schematic originally comes from Bias Comms and was originally intended for use in combination with a BGY33 or BGY133 module. The PLL is very straightforward and should not be too difficult to build.
The synthesizer will generate a 3:1 frequency range anywhere from 300Hz to 4,000,000Hz (4MHz). Using the components shown you can feed the synthesizer with up to 12vDC but with only 9vDC the synthesizer may not achieve more than 3.5MHz.
Lock range extended up to about 400:1 (50KHz - 2MHz). Spectral purity improved - reduced reference frequency FM ripple. Output level buffered to over 200mW RF power output. Unecessary DIP switches removed - silly combinations not possible. BMP format single-sided PCB foil available for downloading. External VCO/Prescaler PCB to follow shortly (up to 150MHz)
This PLL has been designed with an old Motorola circuit :the MC145151.
The VCO is based on a "Colpitz" oscillator equiped with a Fet Transistor.(J310)
Two varicap Diodes are used in order to reduce the global noise of the VCO.
In addition,these two diodes allow the PLL to keep the lock status through a large range of climatic conditions.
An another J310 is used in order to match the impedance between the oscillator and the fist amplifier stage.
A MSA1105 from Minicircuits increases the RF power level coming from the VCO to +14dBm.
A simple low pass filter rejects the second harmonic to -20 dB.(Worst case)
Finally, a 7 dB attenuator and a second amplifier stage (BFR96S) achieve this radio design.
MC145170 PLL Synthesizer with PIC16F84
This schematic originally comes from a Dutch magazine called Free Radio Magazine in the mid eighties. It's just a PLL nothing more, nothing less. The resistor named R can be replaced by a 50 Ohm type if the power supply is 5 Volts. The dividing ratio can be programed with IC2. For the ratios see table 1. Example: If the input signal has a frequency of 10MHz, the crystal frequency output is 10.240-10.000=0.24. Now looking at table 1, we see we can make 24 by combining the 8 and 16 program switches (pin 11 and pin 12 closed to Vcc).
This PLL was first published in March 1983 in Free Radio Magazine and was re-published a year later in the same magazine. It uses the well known 4046 as PLL and a CD4059 as programmable divider.
SAA1057 Dual-speed PLL designed for wideband FM transmitter.
The resistor named R can be replaced by a 50 Ohm type if the power supply is 5 Volts. The dividing ratio can be programed with IC2. For the ratios see table 1. Example: If the input signal has a frequency of 10MHz, the crystal frequency output is 10.240-10.000=0.24. Now looking at table 1, we see we can make 24 by combining the 8 and 16 program switches (pin 11 and pin 12 closed to Vcc). By trimming coil T the output will lock to 10MHz. To use this PLL in the 3 meter band (100MHz), divide the oscillator frequency by 10. Next feed this signal to pin 4 from IC1 by a 8pF capacitor. The adjust voltage coming from IC2 pin 5 should be connected to the oscillator's varicap by a 4k7 resistor. As described here, the PLL will make frequency stepping of 10kHz, to change it to 5kHz apply around minus 9V to pin 4 from IC2. When using this PLL in the 3 meter band, this will result in stepping of 50kHz instead of 100kHz.
Very simple design and will cover the centre frequency plus or minus 20%. It is completely powered by a single 5 volt supply. A 10nf decoupling capacitor is fitted across every IC in the circuit, but there was not enough space in the circuit to show this. Receive frequency is selected with BCD switches & covers the selected band in 1KHz steps. The variable cap in the reference oscillator is varied to "clarify" the received signal. The synthesizer must be tuned to 500KHz above/below the frequency you want to receive if the receiver board is set to 500KHz.
A Phase Locked Loop (PLL) consists of a Voltage Controlled Oscillator (VCO), the output frequency of which is monitored and controlled. An error voltage steers the VCO and brings it back onto the correct frequency. The error voltage is generated by a Phase Sensitive Detector (PSD) which compares the VCO frequency with a reference frequency.
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